This invention relates to devices for signal selecting, and more particularly, to a multiplexer having a pipeline structure.
Multistage tree type multiplexers have the disadvantage that each stage adds additional capacitive loading as well as adding unknown and variable amounts of propagation delay. As a result, in current multiplexers, it may be indeterminable which clock the data is associated with. The present invention overcomes the above mentioned disadvantages for a digital multiplexer by providing a latch at each stage of switching. The latch buffers the input signal, provides restored logic levels at each stage, fixes the delay per stage at the clock period used to clock the latches, and provides a new data bit each clock period.
Thus, the present invention has a fixed delay, i.e. a known delay even though the propagation delay time for selecting a signal through the multiplexer may be increased. Further, the present invention has the advantage of reducing drive requirements by including the latches between stages. The drive requirements of the present invention is one gate level plus the latch, instead of the summation of all the capacitance of all the stages as required by current multiplexers. Data throughput of conventional tree type multiplexers is governed by the propagation delay through the entire tree. However, data throughput of the present invention is limited only by the propagation delay of a single stage. Once the "pipeline" is filled with data (after N clock pulses), new data is output at every clock period.